Electronic devices, such as microprocessors, are steadily operating at faster and faster speeds. As microprocessors run at higher and higher speeds, the power delivered to the microprocessors by a power supply starts to become an issue. Power consumption has become a significant limiter in high-performance microprocessor design. One of the largest components of power consumption is the clocking subsystem, including clock generation, distribution, and clocking power consumed in flop-flops and latches. In order to achieve significant frequency increase, the pipelining depth typically increases with each new processor, hence increasing the number of clocked elements and further adding to the clocking power. At the same time, low jitter and skew requirements of the clock network result in significant distribution power.